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954226 idt ? programmable timing control hub tm for mobile p4 tm systems 0930a?04/13/10 programmable timing control hub tm for mobile p4 tm systems 1 datasheet mlf pin configuration recommended application: ck410m compatible main clock output features: ? 2 - 0.7v current-mode differential cpu pairs ? 4 - 0.7v current-mode differential pci express* pairs ? 1 - 0.7v current-mode differential cpu/pci express selectable pair ? 1 - 0.7v current-mode differential sata pair ? 1 - 0.7v current-mode differential lcdclk/pci express selectable pair ? 4 - pci (33mhz) ? 2 - pciclk_f, (33mhz) free-running ? 1 - usb, 48mhz ? 1 - dot, 96mhz, 0.7v current differential pair ? 2 - ref, 14.318mhz key specifications: ? cpu outputs cycle-cycle jitter < 85ps ? pci express outputs cycle-cycle jitter < 125ps ? sata outputs cycle-cycle jitter < 125ps ? pci outputs cycle-cycle jitter < 500ps ? +/- 300ppm frequency accuracy on cpu, pci express and sata clocks ? +/- 100ppm frequency accuracy on usb clocks features/benefits: ? supports tight ppm accuracy clocks for serial-ata and pci express ? supports programmable spread percentage and frequency ? uses external 14.318mhz crystal, external crystal load caps are required for frequency tuning ? supports undriven differential cpu, pci express pair in pd for power management. ? pereq# pins to support pci express and sata power management. tssop pin configuration gnd pciclk5 pciclk4 pciclk3 gnd vddpci pciclk2/req_sel** pci/src_stop# cpu_stop# ref1/fslc/test_sel ref0 gnd x1 x2 56 55 54 53 52 51 50 49 48 47 46 45 44 43 vddpci 142 vddref itp_en/pciclk_f0 241 sdata **selpciex_lcdclk#/pciclk_f1 340 sclk vtt_pwrgd#/pd 439 gnd vdd48 538 cpuclkt0 fsla/usb_48mhz 637 cpuclkc0 gnd 736 vddcpu dott_96mhz 835 cpuclkt1 dotc_96mhz 934 cpuclkc1 fslb/test_mode 10 33 iref lcdclk_ss/pciext0 11 32 gnda lcdclk_ss/pciexc0 12 31 vdda pciext1 13 30 cpuclkt2_itp/pciext6 pciexc1 14 29 cpuclkc2_itp/pciexc6 15 16 17 18 19 20 21 22 23 24 25 26 27 28 vddpciex pciext2 pciexc2 pciext3 pciexc3 sataclkt sataclkc vddpciex gnd pciexc4 pciext4 pereq2#*/pciexc5 pereq1#*/pciext5 vddpciex ics 954226aklf 56-mlf * internal pull-up resistor ** internal pull-down resistor vddpci 1 56 pciclk2/req_sel** gnd 2 55 pci/src_stop# pciclk3 3 54 cpu_stop# pciclk4 4 53 ref1/fs l c/test_sel pciclk5 5 52 ref0 gnd 6 51 gnd vddpci 7 50 x1 itp_en/pciclk_f0 8 49 x2 **selpciex_lcdclk#/pciclk_f1 9 48 vddref vtt_pwrgd#/pd 10 47 sdata vdd48 11 46 sclk fs l a/usb_48mhz 12 45 gnd gnd 13 44 cpuclkt0 dott_96mhz 14 43 cpuclkc0 dotc_96mhz 15 42 vddcpu fs l b/test_mode 16 41 cpuclkt1 lcdclk_ss/pciex0t 17 40 cpuclkc1 lcdclk_ss/pciex0c 18 39 iref pciext119 38gnda pciexc1 20 37 vdda vddpciex 21 36 cpuclkt2_itp/pciext6 pciext2 22 35 cpuclkc2_itp/pciexc6 pciexc2 23 34 vddpciex pciext3 24 33 pereq1#*/pciext5 pciexc3 25 32 pereq2#*/pciexc5 sataclkt 26 31 pciext4 sataclkc 27 30 pciexc4 vddpciex 28 29 gnd 56-tssop * internal pull-up resistor ** internal pull-down resistor ics954226 table 1: frequency selection table fs l c b6b2 fs l b b6b1 fs l a b6b0 cpu mhz pciex mhz pci mhz ref mhz u sb mhz dot mhz s p read % 0 0 0 266.66 100.00 33.33 14.318 48.00 96.00 0.5% down 0 0 1 133.33 100.00 33.33 14.318 48.00 96.00 0.5% down 0 1 0 200.00 100.00 33.33 14.318 48.00 96.00 0.5% down 0 1 1 166.66 100.00 33.33 14.318 48.00 96.00 0.5% down 1 0 0 333.33 100.00 33.33 14.318 48.00 96.00 0.5% down 1 0 1 100.00 100.00 33.33 14.318 48.00 96.00 0.5% down 1 1 0 400.00 100.00 33.33 14.318 48.00 96.00 0.5% down 1 1 1 200.00 100.00 33.33 14.318 48.00 96.00 0.5% down
idt ? programmable timing control hub tm for mobile p4 tm systems 0930a?04/13/10 954226 programmable timing control hub tm for mobile p4 tm systems 2 tssop pin description pin # pin name type description 1 vddpci pwr power supply for pci clocks, nominal 3.3v 2 gnd pwr ground pin. 3 pciclk3 out pci clock output. 4 pciclk4 out pci clock output. 5 pciclk5 out pci clock output. 6 gnd pwr ground pin. 7 vddpci pwr power supply for pci clocks, nominal 3.3v 8 itp_en/pciclk_f0 i/o free running pci clock not affected by pci_stop# through i2c . itp_en: latched input to select pin functionality 1 = cpu_2_itp pair 0 = pciex_6 pair 9 **selpciex_lcdclk#/pciclk_f1 i/o latched select input for lcdclk/pciex output 0 = lcdclk, 1 = pciex / free running 3.3v pci clock output. 10 vtt_pwrgd#/pd in vtt_pwrgd# is an active low input used to determine when latched inputs are ready to be sampled. pd is an asynchronous active high input pin used to put the device into a low power state. the internal clocks, plls and the crystal oscillator are stopped. 11 vdd48 pwr power pin for the 48mhz output.3.3v 12 fsla/usb_48mhz i/o 3.3v tolerant input for cpu frequency selection. refer to input electrical characteristics for vil_fs and vih_fs values. / fixed 48mhz usb clock output. 3.3v. 13 gnd pwr ground pin. 14 dott_96mhz out true clock of differential pair for 96.00mhz dot clock. 15 dotc_96mhz out complement clock of differential pair for 96.00mhz dot clock. 16 fslb/test_mode in 3.3v tolerant input for cpu frequency selection. refer to input electrical characteristics for vil_fs and vih_fs values. test_mode is a real time input to select between hi-z and ref/n divider mode while in test mode. refer to test clarification table. 17 lcdclk_ss/pciex0t out true clock of lcdclk_ss output / true clock of pci express differential pair. selected by selpciex_lcdclk# 18 lcdclk_ss/pciex0c out complementary clock of lcdclk_ss output / complementary clock of pci express differential pair. selected by selpciex_lcdclk# 19 pciext1 out true clock of differential pci_express pair. 20 pciexc1 out complement clock of differential pci_express pair. 21 vddpciex pwr power supply for pci express clocks, nominal 3.3v 22 pciext2 out true clock of differential pci_express pair. 23 pciexc2 out complement clock of differential pci_express pair. 24 pciext3 out true clock of differential pci_express pair. 25 pciexc3 out complement clock of differential pci_express pair. 26 sataclkt out true clock of differential sata pair. 27 sataclkc out complement clock of differential sata pair. 28 vddpciex pwr power supply for pci express clocks, nominal 3.3v
idt ? programmable timing control hub tm for mobile p4 tm systems 0930a?04/13/10 954226 programmable timing control hub tm for mobile p4 tm systems 3 tssop pin description (cont.) pin # pin name type description 29 gnd pwr ground pin. 30 pciexc4 out complement clock of differential pci_express pair. 31 pciext4 out true clock of differential pci_express pair. 32 pereq2#*/pciexc5 i/o real-time input pin that controls sataclk and pciexclk outputs that are selected through the i2c. 1 = disabled, 0 = enabled. / complement clock of differential pci express output. 33 pereq1#*/pciext5 i/o real-time input pin that controls sataclk and pciexclk outputs that are selected through the i2c. 1 = disabled, 0 = enabled. / true clock of differential pci express output. 34 vddpciex pwr power supply for pci express clocks, nominal 3.3v 35 cpuclkc2_itp/pciexc6 out complementary clock of cpu_itp/pciex differential pair cpu_itp/pciex output. these are current mode outputs. external resistors are required for voltage bias. selected by itp_en input. 36 cpuclkt2_itp/pciext6 out true clock of differential pair cpu outputs. these are current mode outputs. external resistors are required for voltage bias. / true clock of differential pciex pair 37 vdda pwr 3.3v power for the pll core. 38 gnda pwr ground pin for the pll core. 39 iref out this pin establishes the reference current for the differential current-mode output pairs. this pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. 40 cpuclkc1 out complementary clock of differential pair cpu outputs. these are current mode outputs. external resistors are required for voltage bias. 41 cpuclkt1 out true clock of differential pair cpu outputs. these are current mode outputs. external resistors are required for voltage bias. 42 vddcpu pwr supply for cpu clocks, 3.3v nominal 43 cpuclkc0 out complementary clock of differential pair cpu outputs. these are current mode outputs. external resistors are required for voltage bias. 44 cpuclkt0 out true clock of differential pair cpu outputs. these are current mode outputs. external resistors are required for voltage bias. 45 gnd pwr ground pin. 46 sclk in clock pin of smbus circuitry, 5v tolerant. 47 sdata i/o data pin for smbus circuitry, 5v tolerant. 48 vddref pwr ref, xtal power supply, nominal 3.3v 49 x2 out crystal output, nominally 14.318mhz 50 x1 in crystal input, nominally 14.318mhz. 51 gnd pwr ground pin. 52 ref0 out 14.318 mhz reference clock. 53 ref1/fslc/test_sel i/o 14.318 mhz reference clock./ 3.3v tolerant input for cpu frequency selection. refer to input electrical characteristics for vil_fs and vih_fs values. /test_sel: 3-level latched input to enable test mode. refer to test clarification table 54 cpu_stop# in stops all cpuclk, except those set to be free running clocks 55 pci/src_stop# in stops all pciclks and srcclks besides the free-running clocks at logic 0 level, when input low 56 pciclk2/req_sel** i/o 3.3v pci clock output / latch select input pin. 0 = pciexclk, 1 = pereq#
idt ? programmable timing control hub tm for mobile p4 tm systems 0930a?04/13/10 954226 programmable timing control hub tm for mobile p4 tm systems 4 mlf pin description pin # pin name type description 1 vddpci pwr power supply for pci clo cks, nominal 3.3v 2 itp_en/pciclk_f0 i/o free running pci clock not affected by pci_stop#. itp_en: latched input to select pin functionality 1 = cpu_itp pair 0 = src pair 3 **selpciex_lcdclk#/pciclk_f1 i/o latched select input for l cdclk/pciex output 0 = lcdclk, 1 = pciex / free running 3.3v pci clock output. 4 vtt_pwrgd#/pd in vtt_pwrgd# is an active low input used to determine when latched inputs are ready to be sampled. pd is an asynchronous active high input pin used to put the device into a low power state. the internal clocks, plls and the crystal oscillator are st opped. 5 vdd48 pwr power pin for the 48mhz output.3.3v 6 fsla/usb_48mhz i/o 3.3v tolerant input for cpu frequency selection. refer to input electrical characteristics for vil_fs and vih_fs values. / fixed 48mhz usb clock output. 3.3v. 7 gnd pwr ground pin. 8 dott_96mhz out free running pci clock not affected by pci_stop# through i2c . itp_en: latched input to select pin functionality 1 = cpu_2_itp pair 0 = pciex_6 pair 9 dotc_96mhz out complement clock of differential pair for 96.00mhz dot clock. 10 fslb/test_mode in 3.3v tolerant input for cpu frequency selection. refer to input electrical characteristics for vil_fs and vih_fs values. test_mode is a real time input to select between hi-z and ref/n divider mode while in test mode. refer to test clarification table. 11 lcdclk_ss/pciext0 out true clock of lcdclk_ss output / true clock of pci express differential pair. selected by selpciex_lcdclk# 12 lcdclk_ss/pciexc0 out complementary clock of lcdclk_ss output / complementary clock of pci express differential pair. selected by selpciex_lcdclk# 13 pciext1 out true clock of differential pci_express pair. 14 pciexc1 out complement clock of differential pci_express pair. 15 vddpciex pwr power supply for pci express clo cks, nominal 3.3v 16 pciext2 out true clock of differential pci_express pair. 17 pciexc2 out complement clock of differential pci_express pair. 18 pciext3 out true clock of differential pci_express pair. 19 pciexc3 out complement clock of differential pci_express pair. 20 sataclkt out true clock of differential sata pair. 21 sataclkc out complement clock of differential sata pair. 22 vddpciex pwr power supply for pci express clo cks, nominal 3.3v 23 gnd pwr ground pin. 24 pciexc4 out complement clock of differential pci_express pair. 25 pciext4 out true clock of differential pci_express pair. 26 pereq2#*/pciexc5 i/o real-time input pin that controls sataclk and pciexclk outputs that are selected through the i2c. 1 = disabled, 0 = enabled. / complement clock of differential pci express output. 27 pereq1#*/pciext5 i/o real-time input pin that controls sataclk and pciexclk outputs that are selected through the i2c. 1 = disabled, 0 = enabled. / true clock of differential pci express output. 28 vddpciex pwr power supply for pci express clo cks, nominal 3.3v
idt ? programmable timing control hub tm for mobile p4 tm systems 0930a?04/13/10 954226 programmable timing control hub tm for mobile p4 tm systems 5 mlf pin description (continued) pin # pin name type description 29 cpuclkc2_itp/pciexc6 out complementary clock of cpu_itp/pciex differential pair cpu_itp/pciex output. these are current mode outputs. external resistors are required for voltage bias. selected by itp_en input. 30 cpuclkt2_itp/pciext6 out true clock of differential pair cpu outputs. these are current mode outputs. external resistors are required for voltage bias. / true clock of differential pciex pair 31 vdda pwr 3.3v power for the pll core. 32 gnda pwr ground pin for the pll core. 33 iref out this pin establishes the reference current for the differential current-mode output pairs. this pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. 34 cpuclkc1 out complementary clock of differential pair cpu outputs. these are current mode outputs. external resistors are required for voltage bias. 35 cpuclkt1 out true clock of differential pair cpu outputs. these are current mode outputs. external resistors are required for voltage bias. 36 vddcpu pwr supply for cpu clo cks, 3.3v nominal 37 cpuclkc0 out complementary clock of differential pair cpu outputs. these are current mode outputs. external resistors are required for voltage bias. 38 cpuclkt0 out true clock of differential pair cpu outputs. these are current mode outputs. external resistors are required for voltage bias. 39 gnd pwr ground pin. 40 sclk in clock pin of smbus circuitry, 5v tolerant. 41 sdata i/o data pin for smbus circuitry, 5v tolerant. 42 vddref pwr ref, xtal power s upply, nominal 3.3v 43 x2 out crystal output, nominally 14.318mhz 44 x1 in crystal input, nominally 14.318mhz. 45 gnd pwr ground pin. 46 ref0 out 14.318 mhz reference clock. 47 ref1/fslc/test_sel i/o 14.318 mhz reference clock./ 3.3v tolerant input for cpu frequency selection. refer to input electrical characteristics for vil_fs and vih_fs values. /test_sel: 3-level latched input to enable test mode. refer to test clarification table 48 cpu_stop# in stops all cpuclk, except those set to be free running clocks 49 pci/src_stop# in stops all pciclks and srcclks besides the free-running clo cks at logic 0 level, when input low 50 pciclk2/req_sel** i/o 3.3v pci clock output / latch select input pin. 0 = pciexclk, 1 = pereq# 51 vddpci pwr power supply for pci clo cks, nominal 3.3v 52 gnd pwr ground pin. 53 pciclk3 out pci clock output. 54 pciclk4 out pci clock output. 55 pciclk5 out pci clock output. 56 gnd pwr ground pin.
idt ? programmable timing control hub tm for mobile p4 tm systems 0930a?04/13/10 954226 programmable timing control hub tm for mobile p4 tm systems 6 block diagram the ics954226 is a ck410m compatible clock synthesizer. it provides a single-chip solution for mobile systems built with intel p4-m processors and intel mobile chipsets. the device is driven with a 14.318mhz crystal and generates cpu outputs up to 400mhz. it provides the tight ppm accuracy required by serial ata and pci express. general description prog. spread main pll pciclk(5:2) control logic xtal osc. fixed pll usb_48mhz divider pr og. divider s ref(1:0) pciex(5:1) itp_en s data sclk selpciex_lcdclk# req_sel test_mode test_sel x1 x2 iref fsl(c:a) vtt_pwrgd#/pd dot_ 9 6mhz cpuclk(1:0) lcdclk_ss/pciex0 sataclk pciclk_f(1:0) cpuclk2/pciex6 pci/src_stop# cpu_stop# pereq#(2:1)
idt ? programmable timing control hub tm for mobile p4 tm systems 0930a?04/13/10 954226 programmable timing control hub tm for mobile p4 tm systems 7 table2: lcdclk spread and frequency selection table pin 17/18 mhz 0 0 0 0 0 96.00 0 0 0 0 1 96.00 0 0 0 1 0 96.00 0 0 0 1 1 96.00 0 0 1 0 0 96.00 0 0 1 0 1 96.00 0 0 1 1 0 96.00 0 0 1 1 1 96.00 0 1 0 0 0 96.00 0 1 0 0 1 96.00 0 1 0 1 0 96.00 0 1 0 1 1 96.00 0 1 1 0 0 96.00 0 1 1 0 1 96.00 0 1 1 1 0 96.00 0 1 1 1 1 96.00 10000100.00 10001100.00 10010100.00 10011100.00 10100100.00 10101100.00 10110100.00 10111100.00 11000100.00 11001100.00 11010100.00 11011100.00 11100100.00 11101100.00 11110100.00 11111 100.00 byte 6b7 byte 6b6 byte 6b5 byte 6b4 byte 6b3 spread % 0.8 down 1 down 1.25 down 1.75 down 1.5 down 2.5 down 2 down 3 down +/-0.3 center +/-0.4 center +/-0.5 center +/-0.6 center +/-0.8 center +/-1.0 center +/-1.25 center +/-1.5 center 0.8 down 1 down 1.25 down 1.5 down 1.75 down 2 down 2.5 down 3 down +/-0.3 center +/-1.0 center +/-1.25 cente r +/-1.5 center +/-0.4 center +/-0.5 center +/-0.6 center +/-0.8 center
idt ? programmable timing control hub tm for mobile p4 tm systems 0930a?04/13/10 954226 programmable timing control hub tm for mobile p4 tm systems 8 general smbus serial interface information for the 954226 * by default, smbadr = 0, therefore, smbus write/read address is d0/d1. please see smbus address selection table on page 1. how to write: ? controller (host) sends a start bit. ? controller (host) sends the write address d2 (h) ? ics clock will acknowledge ? controller (host) sends the begining byte location = n ? ics clock will acknowledge ? controller (host) sends the data byte count = x ? ics clock will acknowledge ? controller (host) starts sending byte n through byte n + x -1 (see note 2) ? ics clock will acknowledge each byte one at a time ? controller (host) sends a stop bit how to read: ? controller (host) will send start bit. ? controller (host) sends the write address d2 (h) ? ics clock will acknowledge ? controller (host) sends the begining byte location = n ? ics clock will acknowledge ? controller (host) will send a separate start bit. ? controller (host) sends the read address d3 (h) ? ics clock will acknowledge ? ics clock will send the data byte count = x ? ics clock sends byte n + x -1 ? ics clock sends byte 0 through byte x (if x (h) was written to byte 8) . ? controller (host) will need to acknowledge each byte ? controllor (host) will send a not acknowledge bit ? controller (host) will send a stop bit ics (slave/receiver) t wr ack ack ack ack ack p stop bit x byte index block write operation slave address d2 (h) beginning byte = n write start bit controller (host) byte n + x - 1 data byte count = x beginning byte n t start bit wr write rt repeat start rd read beginning byte n byte n + x - 1 n not acknowledge pstop bit slave address d3 (h) index block read operation slave address d2 (h) beginning byte = n ack ack data byte count = x ack ics (slave/receiver) controller (host) x byte ack ack
idt ? programmable timing control hub tm for mobile p4 tm systems 0930a?04/13/10 954226 programmable timing control hub tm for mobile p4 tm systems 9 smbus table: output control register control function bit 7 cpuclk2_itp/pciex6 enable output enable rw 1 bit 6 pciex5 enable output enable rw 1 bit 5 pciex4 enable output enable rw 1 bit 4 sataclk enable output enable rw 1 bit 3 pciex3 enable output enable rw 1 bit 2 pciex2 enable output enable rw 1 bit 1 pciex1 enable output enable rw 1 bit 0 lcdclk/pciex0 enable output enable rw 1 smbus table: spread and output control register control function bit 7 test clock mode entry test mode rw 0 bit 6 dot_96mhz enable output enable rw 1 bit 5 usb_48mhz enable output enable rw 1 bit 4 ref_0 enable output enable rw 1 bit 3 lcdclk/pciex0 spectrum mode spread control rw 1 bit 2 cpuclk1 output enable rw 1 bit 1 cpuclk0 output enable rw 1 bit 0 spread spectrum mode spread control for pll1 rw 0 smbus table: output control register control function bit 7 pciclk5 output enable rw 1 bit 6 pciclk4 output enable rw 1 bit 5 pciclk3 output enable rw 1 bit 4 pciclk2 output enable rw 1 bit 3 test mode selection test mode selection rw 0 bit 2 pci_stop stop all pci, pciex and sata clocks rw 1 bit 1 pci_f0 enable output enable rw 1 bit 0 pci_f1 enable output enable rw 1 smbus table: output control register control function bit 7 pciex6 rw 0 bit 6 pciex5 rw 0 bit 5 pciex4 rw 0 bit 4 sataclk rw 0 bit 3 pciex3 rw 0 bit 2 pciex2 rw 0 bit 1 pciex1 rw 0 bit 0 pciex0 rw 0 disable enable disable enable disable enable off on - disable enable disable enable enable disable enable disable - - enable disable enable - - - - - disable enable enable enable off disable disable on pwd 01 byte 1 pin # name type - - - - - - disable enable 01 disable enable pwd - byte 0 pin # name type - disable - free running - allow assertion of pci_stop# or setting of pci_stop control bit in smbus register to stop pciex clocks free running free running stoppable stoppable free running stoppable - - enable stoppable disable disable - - enable pwd pwd stoppable enable 1 enable stoppable disable stoppable enable 0 disable byte 2 pin # name type - 0 disable byte 3 hi-z pin # name type disable - - - - - - - - - disable free running stoppable free running enable 1 ref/n free running free running enable
idt ? programmable timing control hub tm for mobile p4 tm systems 0930a?04/13/10 954226 programmable timing control hub tm for mobile p4 tm systems 10 smbus table: output control register control function bit 7 ref_1 enable output enable rw 1 bit 6 96mhz driven in pd rw 1 bit 5 ref_0 strength strength programming rw 1 bit 4 pci_f1 rw 0 bit 3 pci_f0 rw 0 bit 2 cpuclk2_itp rw 1 bit 1 cpuclk1 rw 1 bit 0 cpuclk0 rw 1 smbus table: output control register control function bit 7 pci_stop drive mode driven in pci_stop# rw 0 bit 6 cpuclk2_itp_stop drive mode rw 0 bit 5 cpuclk1_stop drive mode rw 0 bit 4 cpuclk0_stop drive mode rw 0 bit 3 pciex (6:0) drive mode rw 0 bit 2 cpuclk2_itp_pd drive mode rw 0 bit 1 cpuclk[1:0] pd drive mode rw 0 bit 0 itp_en pciex/cpu_itp select rw latch smbus table: output control register control function bit 7 ss4 lcdclk spread prog bit 4 rw 0 bit 6 ss3 lcdclk spread prog bit 3 rw 1 bit 5 ss2 lcdclk spread prog bit 2 rw 0 bit 4 ss1 lcdclk spread prog bit 1 rw 0 bit 3 ss0 lcdclk spread prog bit 0 rw 0 bit 2 fslc freq select bit 2 rw latched bit 1 fslb freq select bit 1 rw latched bit 0 fsla freq select bit 0 rw latched smbus table: vendor & revision id register control function bit 7 rid3 r x bit 6 rid2 r x bit 5 rid1 r x bit 4 rid0 r x bit 3 vid3 r 0 bit 2 vid2 r 0 bit 1 vid1 r 0 bit 0 vid0 r 1 - -- - vendor id -- - -- - -- - -- - -- 1pwd - revision id -- - -- stoppable free running byte 7 pin # name type 0 - pin # name - driven driven hi-z driven 2x 1 hi-z hi-z stoppable stoppable stoppable - pin # driven in powerdown (pd) allow assertion of cpu_stop# to stop cpuclk outputs - name - - - driven in cpu_stop# allow assertion of pci_stop# or setting of see table 1: pll1 frequency selection table free running hi-z 0 driven see table 2: lcdclk freq sel type free running hi-z disable driven 1 96mhz 100mhz driven driven free running driven pciex enable stoppable hi-z pwd hi-z 1 hi-z cpu_itp type pwd type 0 free running 0 1x pwd - - - - - - - - byte 5 - - byte 4 - - - - - - - byte 6 pin # name
idt ? programmable timing control hub tm for mobile p4 tm systems 0930a?04/13/10 954226 programmable timing control hub tm for mobile p4 tm systems 11 smbus table: byte count register control function bit 7 bc7 rw 0 bit 6 bc6 rw 0 bit 5 bc5 rw 0 bit 4 bc4 rw 0 bit 3 bc3 rw 1 bit 2 bc2 rw 1 bit 1 bc1 rw 1 bit 0 bc0 rw 1 smbus table: watchdog timer register control function bit 7 wdh_en watchdog hard alarm enable rw 0 bit 6 wds_en watchdog soft alarm enable rw 0 bit 5 wd hard status wd hard alarm status r x bit 4 wd soft status wd soft alarm status r x bit 3 wdtctrl watch dog time base control rw 0 bit 2 wd2 wd timer bit 2 rw 1 bit 1 wd1 wd timer bit 1 rw 1 bit 0 wd0 wd timer bit 0 rw 1 smbus table: vco control select bit & wd timer control register control function bit 7 m/n_en pllm/n programming enable rw 0 bit 6 lcdclk/pciex0 sel selpciex0/lcdclk# rw latch bit 5 req_sel req_sel rw latch bit 4 lcdclk/pciex0 driven in pd rw 0 bit 3 wd safe freq source wd safe freq source rw 0 bit 2 wd sfc rw 0 bit 1 wd sfb rw 0 bit 0 wd sfa rw 0 smbus table: vco frequency control register control function bit 7 n div8 n divider prog bit 8 rw x bit 6 n div 9 n divider prog bit 9 rw x bit 5 m div5 rw x bit 4 m div4 rw x bit 3 m div3 rw x bit 2 m div2 rw x bit 1 m div1 rw x bit 0 m div0 rw x alarm m divider programming bits lcdclk pciex0 - - the decimal representation of m and n divier in byte 11 and 12 will configure the vco frequency. default at power up = latch-in or byte 0 rom table. vco frequency = 14.318 x [ndiv(9:0)+8] / [mdiv(5:0)+2] 1 0 - pwd type name watch dog safe freq programming bits writing to these bit will configure the safe frequency as byte0 bit (4:0). pwd - pciex5 pereq byte 10 pin # name - normal normal - - latch inputs/byte6[2:0] these bits represent x*290ms (or 1.16s) the watchdog timer waits before it goes to alarm mode. default is 7 x 290ms = 2s. 290ms base b10b(2:0) name type 0 disable pwd pwd 1 1 byte 8 name type - byte count programming b(7:0) - - - - - - - - - - - - - - byte 9 pin # - - - - - - - - - - pin # byte 11 pin # 0 writing to this register will configure how many bytes will be read back, default is 0f = 15 bytes. type 0 1 1160ms base enable disable driven hi-z disable enable alarm enable
idt ? programmable timing control hub tm for mobile p4 tm systems 0930a?04/13/10 954226 programmable timing control hub tm for mobile p4 tm systems 12 smbus table: vco frequency control register control function bit 7 n div7 rw x bit 6 n div6 rw x bit 5 n div5 rw x bit 4 n div4 rw x bit 3 n div3 rw x bit 2 n div2 rw x bit 1 n div1 rw x bit 0 n div0 rw x smbus table: spread spectrum control register control function bit 7 ssp7 rw x bit 6 ssp6 rw x bit 5 ssp5 rw x bit 4 ssp4 rw x bit 3 ssp3 rw x bit 2 ssp2 rw x bit 1 ssp1 rw x bit 0 ssp0 rw x smbus table: spread spectrum control register control function bit 7 reserved reserved r 0 bit 6 ssp14 rw x bit 5 ssp13 rw x bit 4 ssp12 rw x bit 3 ssp11 rw x bit 2 ssp10 rw x bit 1 ssp9 rw x bit 0 ssp8 rw x smbus table: output divider control register control function bit 7 pciex div3 rw 0000:/2 0100:/4 1000:/8 1100:/16 x bit 6 pciex div2 rw 0001:/3 0101:/6 1001:/12 1101:/24 x bit 5 pciex div1 rw 0010:/5 0110:/10 1010:/20 1110:/40 x bit 4 pciex div0 rw 0011:/15 0111:/30 1011:/60 1111:/120 x bit 3 cpu div3 rw 0000:/2 0100:/4 1000:/8 1100:/16 x bit 2 cpu div2 rw 0001:/3 0101:/6 1001:/12 1101:/24 x bit 1 cpu div1 rw 0010:/5 0110:/10 1010:/20 1110:/40 x bit 0 cpu div0 rw 0011:/15 0111:/30 1011:/60 1111:/120 x 0 - type 1 type these spread spectrum bits in byte 13 and 14 will program the spread pecentage. it is recommended to use ics spread % table for spread programming. these spread spectrum bits in byte 13 and 14 will program the spread pecentage. it is recommended to use ics spread % table for spread programming. 1 spread spectrum programming b(7:0) n divider programming b(8:0) 1 1 byte 12 - - - cpudivider ratio programming bits pciex divider ratio programming bits pwd name type 0 pwd name type name pwd 0 - - - name pin # - - - - - pwd 0 byte 13 pin # - byte 14 pin # - - - - - - - - - - - - - - pin # - - - byte 15 - - - spread spectrum programming b(14:8) the decimal representation of m and n divier in byte 11 and 12 will configure the vco frequency. default at power up = latch-in or byte 0 rom table. vco frequency = 14.318 x [ndiv(9:0)+8] / [mdiv(5:0)+2] -
idt ? programmable timing control hub tm for mobile p4 tm systems 0930a?04/13/10 954226 programmable timing control hub tm for mobile p4 tm systems 13 smbus table: pereq# control register control function bit 7 reserved reserved rw 0 bit 6 pciex4 is controlled rw 0 bit 5 pciex3 is controlled rw 0 bit 4 pciex1 is controlled rw 0 bit 3 reserved reserved rw 0 bit 2 sataclk is controlled rw 0 bit 1 pciex2 is controlled rw 0 bit 0 pciex0 is controlled rw 0 smbus table: pll 2 vco frequency control register control function bit 7 n div8 n divider prog bit 8 rw x bit 6 n div9 n divider prog bit 9 rw x bit 5 m div5 rw x bit 4 m div4 rw x bit 3 m div3 rw x bit 2 m div2 rw x bit 1 m div1 rw x bit 0 m div0 rw x smbus table: pll 2 vco frequency control register control function bit 7 n div7 rw x bit 6 n div6 rw x bit 5 n div5 rw x bit 4 n div4 rw x bit 3 n div3 rw x bit 2 n div2 rw x bit 1 n div1 rw x bit 0 n div0 rw x smbus table: pll 2 spread spectrum control register control function bit 7 ssp7 rw x bit 6 ssp6 rw x bit 5 ssp5 rw x bit 4 ssp4 rw x bit 3 ssp3 rw x bit 2 ssp2 rw x bit 1 ssp1 rw x bit 0 ssp0 rw x -- 1 not controlled controlled 1 the decimal representation of m and n divier in byte 17 and 18 will configure the vco frequency. default at power up = byte 0 rom table. vco frequency = 14.318 x [ndiv(9:0)+8] / [mdiv(5:0)+2] the decimal representation of m and n divier in byte 17 and 18 will configure the vco frequency. default at power up = byte 0 rom table. vco frequency = 14.318 x [ndiv(9:0)+8] / [mdiv(5:0)+2] controlled not controlled controlled not controlled name type m divider programming bits type - - byte 19 pin # spread spectrum programming b(7:0) these spread spectrum bits in byte 19 and 20 will program the spread pecentage. it is recommended to use ics spread % table for spread programming. pwd pwd 01 pwd 0 0 pwd name type 0 1 pin # byte 16 - - type - - - - pin # name pereq2# controls selected outputs. outputs controlled by this pin will be hi-z when pereq2# is high. pereq1# controls selected outputs. outputs controlled by this pin will be hi-z when pereq1# is high. - - - - - - byte 17 - - - - - - - - - - - - - - - - n divider programming b(8:0) - byte 18 pin # name - controlled controlled controlled - not controlled not controlled not controlled -
idt ? programmable timing control hub tm for mobile p4 tm systems 0930a?04/13/10 954226 programmable timing control hub tm for mobile p4 tm systems 14 smbus table: pll2 spread spectrum control register control function bit 7 reserved reserved r 0 bit 6 ssp14 rw x bit 5 ssp13 rw x bit 4 ssp12 rw x bit 3 ssp11 rw x bit 2 ssp10 rw x bit 1 ssp9 rw x bit 0 ssp8 rw x byte 20 pin # name - - - spread spectrum programming b(14:8) pwd type 1 -- 0 these spread spectrum bits in byte 19 and 20 will program the spread pecentage. it is recommended to use ics spread % table for spread programming. - - - - -
idt ? programmable timing control hub tm for mobile p4 tm systems 0930a?04/13/10 954226 programmable timing control hub tm for mobile p4 tm systems 15 electrical characteristics - input/supply/common output parameters parameter symbol conditions* min typ max units notes input high voltage v ih 3.3 v +/-5% 2 v dd + 0.3 v1 input low voltage v il 3.3 v +/-5% v ss - 0.3 0.8 v 1 input high current i ih v in = v d d -5 5 ua 1 i il1 v in = 0 v; inputs with no pull-up resistors -5 ua 1 i il2 v in = 0 v; inputs with pull-up resistors -200 ua 1 low threshold input- high voltage v ih_fsl 3.3 v +/-5% 0.7 1.7 v 1 low threshold input- low voltage v il_fsl 3.3 v +/-5% v ss - 0.3 0.35 v 1 operating supply current i dd3. 3op full active, c l = full load; 400 ma 1 all diff pairs driven 70 ma 1 all differential pairs tri-stated 12 ma 1 input frequency f i v d d = 3.3 v 14.31818 mhz 2 pin inductance l p in 7nh1 c in logic inputs 5 pf 1 c ou t output pin capacitance 6 pf 1 c inx x1 & x2 pins 5 pf 1 clk stabilization t stab from v dd power-up or de-assertion of pd# to 1st clock 1.8 ms 1 modulation frequency triangular modulation 30 33 khz 1 tdrive_pd# cpu output enable after pd# de-assertion 300 us 1 tfall_pd# pd# fall time of 5 ns 1 trise_pd# pd# rise time of 5 ns 1 smbus voltage v d d 2.7 5.5 v 1 low-level output voltage v ol @ i pullup 0.4 v 1 current sinking at v ol = 0.4 v i pullup 4ma1 sclk/sdata clock/data rise time t ri 2c (max vil - 0.15) to (min vih + 0.15) 1000 ns 1 sclk/sdata clock/data fall time t fi 2c (min vih + 0.15) to (max vil - 0.15) 300 ns 1 *ta = 0 - 70c; supply voltage vdd = 3.3 v +/-5% 1 guaranteed by design and characterization, not 100% tested in production. 2 input frequency should be measured at the ref pin and tuned to ideal 14.31818mhz to meet ppm frequency accuracy on pll outputs. input low current powerdown current i dd3. 3pd input capacitance absolute maximum rating parameter symbol conditions min typ max units notes 3.3v core supply voltage vdda - 4.6 v 1 3.3v lo g ic input supply voltage vdd - 4.6 v 1 storage temperature ts - -65 150 c 1 ambient operating temp tambient - 070c 1 junction temperature tj - 125 c 1 input esd protection hbm esd prot - 2000 v 1 1 guaranteed by design and characterization, not 100% tested in production.
idt ? programmable timing control hub tm for mobile p4 tm systems 0930a?04/13/10 954226 programmable timing control hub tm for mobile p4 tm systems 16 electrical characteristics - cpuclkt/c -- 0.7v current mode differential pair parameter symbol conditions* min typ max units notes current source output impedance zo vo = vx 3000 ? 1 voltage high vhigh 660 850 mv 1,3 voltage low vlow -150 150 mv 1,3 max voltage vovs 1150 mv 1 min voltage vuds -300 mv 1 crossing voltage (abs) vx(abs) 250 550 mv 1 crossing voltage (var) d-vx variation of crossing over all edges 140 mv 1 long accuracy ppm see tperiod min-max values -300 300 ppm 1,2 400mhz nominal 2.4993 2.5008 ns 2 400mhz spread 2.4993 2.5133 ns 2 333.33mhz nominal 2.9991 3.0009 ns 2 333.33mhz spread 2.9991 3.016 ns 2 266.66mhz nominal 3.7489 3.7511 ns 2 266.66mhz spread 3.7489 3.77 ns 2 200mhz nominal 4.9985 5.0015 ns 2 200mhz spread 4.9985 5.0266 ns 2 166.66mhz nominal 5.9982 6.0018 ns 2 166.66mhz spread 5.9982 6.0320 ns 2 133.33mhz nominal 7.4978 7.5023 ns 2 133.33mhz spread 7.4978 7.5400 ns 2 100.00mhz nominal 9.9970 10.0030 ns 2 100.00mhz spread 9.9970 10.0533 ns 2 400mhz nominal/spread 2.4143 ns 1,2 333.33mhz nominal/spread 2.9141 ns 1,2 266.66mhz nominal/spread 3.6639 ns 1,2 200mhz nominal/spread 4.8735 ns 1,2 166.66mhz nominal/spread 5.8732 ns 1,2 133.33mhz nominal/spread 7.3728 ns 1,2 100.00mhz nominal/spread 9.8720 ns 1,2 rise time tr vol = 0.175v, voh = 0.525v 175 700 ps 1 fall time tf voh = 0.525v vol = 0.175v 175 700 ps 1 rise time variation d-tr vol = 0.175v, voh = 0.525v 125 ps 1 fall time variation d-tf voh = 0.525v vol = 0.175v 125 ps 1 rise/fall matching trfm 20 % 1 duty cycle dt3 measurement from differential wavefrom 45 55 % 1 skew tsk3 cpu(1:0), vt = 50% 100 ps 1 skew tsk4 cpu(1:0) to cpu2_itp, vt = 50% 150 ps 1 jitter, cycle to cycle tjcyc-cyc measurement from differential wavefrom (cpu2_itp) 125 ps 1 jitter, cycle to cycle tjcyc-cyc measurement from differential wavefrom, (cpu(1:0)) 85 ps 1 *t a = 0 - 70c; v dd = 3.3 v +/-5%; c l =2pf, r s =33.2 ? , r p =49.9 ? , i ref = 475 ? 1 guaranteed by design and characterization, not 100% tested in production. 2 all long term accuracy and clock period specifications are guaranteed assuming that refout is at 14.31818mhz 3 i ref = v dd /(3xr r ). for r r = 475 ? (1%), i ref = 2.32ma. i oh = 6 x i ref and v oh = 0.7v @ z o =50 ? . statistical measurement on single ended signal measurement on single ended signal using absolute value. average period tperiod absolute min period tabsmin
idt ? programmable timing control hub tm for mobile p4 tm systems 0930a?04/13/10 954226 programmable timing control hub tm for mobile p4 tm systems 17 electrical characteristics - sata/pciex/lcdclk_ss@100m 0.7v current mode differential pair parameter symbol conditions* min typ max units notes current source output impedance zo vo = vx 3000 ? 1 voltage high vhigh 660 850 mv 1,3 voltage low vlow -150 150 mv 1,3 max voltage vovs 1150 mv 1 min volta g e vuds -300 mv 1 crossing voltage (abs) vx(abs) 250 550 mv 1 crossing voltage (var) d-vx variation of crossing over all edges 140 mv 1 long accuracy ppm see tperiod min-max values -300 300 ppm 1,2 100.00mhz nominal 9.9970 10.0030 ns 2 100.00mhz spread 9.9970 10.0533 ns 2 absolute min period tabsmin 100.00mhz nominal/spread 9.8720 ns 1,2 rise time tr vol = 0.175v, voh = 0.525v 175 700 ps 1 fall time tf voh = 0.525v vol = 0.175v 175 700 ps 1 rise time variation d-tr vol = 0.175v, voh = 0.525v 125 ps 1 fall time variation d-tf voh = 0.525v vol = 0.175v 125 ps 1 rise/fall matching trfm 20 % 1 duty cycle dt3 measurement from differential wavefrom 45 55 % 1 skew tsk3 vt = 50% 250 ps 1 jitter, cycle to cycle tjcyc-cyc measurement from differential wavefrom 125 ps 1 *t a = 0 - 70c; v dd = 3.3 v +/-5%; c l =2pf, r s =33.2 ? , r p =49.9 ? i ref = 475 ? 1 guaranteed by design and characterization, not 100% tested in production. 2 all long term accuracy and clock period specifications are guaranteed assuming that refout is at 14.31818mhz 3 i ref = v dd /(3xr r ). for r r = 475 ? (1%), i ref = 2.32ma. i oh = 6 x i ref and v oh = 0.7v @ z o =50 ? . statistical measurement on single ended signal measurement on single ended signal usin g absolute value. average period tperiod electrical characteristics - dot_96mhz/lcdclk_ss@96m 0.7v current mode differential pair parameter symbol conditions* min typ max units notes current source output impedance zo vo = vx 3000 ? 1 voltage high vhigh 660 850 mv 1,3 voltage low vlow -150 150 mv 1,3 max voltage vovs 1150 mv 1 min voltage vuds -300 mv 1 crossing voltage (abs) vx(abs) 250 550 mv 1 crossing voltage (var) d-vcross variation of crossing over all edges 140 mv 1 long accuracy ppm see tperiod min-max values -100 100 ppm 1,2 average period tperiod 96.00mhz nominal 10.4135 10.4198 ns 2 absolute min period tabsmin 96.00mhz nominal 10.1635 ns 1,2 rise time tr vol = 0.175v, voh = 0.525v 175 700 ps 1 fall time tf voh = 0.525v vol = 0.175v 175 700 ps 1 rise time variation d-tr vol = 0.175v, voh = 0.525v 125 ps 1 fall time variation d-tf voh = 0.525v vol = 0.175v 125 ps 1 rise/fall matching trfm 20 % 1 duty cycle dt3 measurement from differential wavefrom 45 55 % 1 jitter, cycle to cycle tjcyc-cyc measurement from differential wavefrom 250 ps 1 *t a = 0 - 70c; v dd = 3.3 v +/-5%; c l =2pf, r s =33.2 ? , r p =49.9 ? i ref = 475 ? 1 guaranteed by design and characterization, not 100% tested in production. 2 all long term accuracy and clock period specifications are guaranteed assuming that refout is at 14.31818mhz 3 i ref = v dd /(3xr r ). for r r = 475 ? (1%), i ref = 2.32ma. i oh = 6 x i ref and v oh = 0.7v @ z o =50 ? . measurement on single ended signal using absolute value. statistical measurement on single ended signal
idt ? programmable timing control hub tm for mobile p4 tm systems 0930a?04/13/10 954226 programmable timing control hub tm for mobile p4 tm systems 18 electrical characteristics - pciclk/pciclk_f parameter symbol conditions* min typ max units notes output impedance r dsp v o = v d d *(0.5) 12 55 ? 1 output high voltage v oh i oh = -1 ma 2.4 v 1 output low voltage v ol i ol = 1 ma 0.55 v 1 v oh @min = 1.0 v -33 ma 1 v oh @max = 3.135 v -33 ma 1 v ol @ min = 1.95 v 30 ma 1 v ol @ max = 0.4 v 38 ma 1 edge rate t slewr/f rising/falling edge rate vol = 0.4 v, voh = 2.4 v 14v/ns1 duty cycle d t1 v t = 1.5 v 45 55 % 1 group skew t skew v t = 1.5 v 500 ps 1 jitter, cycle to cycle t j c y c-c y c v t = 1.5 v 250 ps 1 *ta = 0 - 70c; supply voltage vdd = 3.3 v +/-5%, cl = 5 pf with rs = 33 ? (unless otherwise specified) 1 guaranteed by design and characterization, not 100% tested in production. output high current i oh output low current i ol electrical characteristics - 48mhz parameter symbol conditions* min typ max units notes long accuracy ppm see tperiod min-max values -100 100 ppm 1 clock period t p eriod 48.00mhz output nominal 20.8313 20.8354 ns output impedance r dsp v o = v d d *(0.5) 12 55 ? 1 output high voltage v oh i oh = -1 ma 2.4 v 1 output low voltage v ol i ol = 1 ma 0.55 v 1 v oh @min = 1.0 v -33 ma 1 v oh @max = 3.135 v -33 ma 1 v ol @ min = 1.95 v 30 ma 1 v ol @ max = 0.4 v 38 ma 1 edge rate t slewr/f_48 48m rising/falling edge rate vol = 0.4 v, voh = 2.4 v 12v/ns1 duty cycle d t1 v t = 1.5 v 45 55 % 1 jitter, cycle to cycle t j c y c-c y c v t = 1.5 v 500 ps 1 *ta = 0 - 70c; supply voltage vdd = 3.3 v +/-5%, cl = 5 pf with rs = 33 ? 1 guaranteed by design and characterization, not 100% tested in production. output high current i oh output low current i ol electrical characteristics - ref-14.318mhz parameter symbol conditions min typ max units notes long accuracy ppm see tperiod min-max values -300 300 ppm 1,2 clock period tperiod 14.318mhz output nominal 69.8270 69.8550 ns 2 output high voltage voh ioh = -1 ma 2.4 v 1 output low voltage vol iol = 1 ma 0.4 v 1 output high current ioh voh @min = 1.0 v, voh@max = 3.135 v -29 -23 ma 1 output low current iol vol @min = 1.95 v, vol @max = 0.4 v 29 27 ma 1 edge rate tslewr/f rising/falling edge rate vol = 0.4 v, voh = 2.4 v 14v/ns1 duty cycle dt1 vt = 1.5 v 45 55 % 1 jitter tjcyc-cyc vt = 1.5 v 1000 ps 1 *ta = 0 - 70c; supply voltage vdd = 3.3 v +/-5%, cl = 5 pf with rs = 39 ? 1 guaranteed by design and characterization, not 100% tested in production. 2 all long term accuracy and clock period specifications are guaranteed assuming that refout is at 14.31818mhz
idt ? programmable timing control hub tm for mobile p4 tm systems 0930a?04/13/10 954226 programmable timing control hub tm for mobile p4 tm systems 19 test clarification table comments fslc/tes t_sel hw pin fslb/tes t_mode hw pin test entry bit w1b7 ref/n or hi-z w2b3 output 0x0xnormal 10x0hi-z 10x1ref/n 11x0ref/n 11x1ref/n 0x10hi-z 0x11ref/n w1b7: 1= enter test mode, default = 0 (normal operation) w2b3: 1= ref/n, default = 0 (hi-z) h w s w f s _ c/ te s t_ s el is a 3-level latched input. o power-up w/ v >= 2.0v to select test o power-up w/ v < 2.0v to have pin function as fs_c. when pin is fs_c, vih_fs and vil_fs levels apply. fs_b/test_mode is a low-threshold input o vih_fs and vil_fs levels apply. o test_mode is a real time input test_sel can be invoked after power up through smbus b1b7. o if test is selected by b1b7, only b2b3 controls test_mode. the fs_b/test_mode pin is not used. power must be cycled to exit test.
idt ? programmable timing control hub tm for mobile p4 tm systems 0930a?04/13/10 954226 programmable timing control hub tm for mobile p4 tm systems 20 index area index area 12 1 2 n d e1 e seating plane seating plane a1 a a2 e -c- - c - b c l aaa c min max min max a -- 1.20 -- .047 a1 0.05 0.15 .002 .006 a2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 d e e1 6.00 6.20 .236 .244 e l 0.45 0.75 .018 .030 n a0808 aaa -- 0.10 -- .004 variations min max min max 56 13.90 14.10 .547 .555 10-0039 56-lead 6.10 mm. bod y , 0.50 mm. pitch tssop ( 240 mil ) ( 20 mil ) symbol in millimeters in inches common dimensions common dimensions see variations see variations 8.10 basic 0.319 basic 0.50 basic 0.020 basic see variations see variations n d mm. d (inch) ref erence do c.: jedec pub licat io n 9 5, m o-153
idt ? programmable timing control hub tm for mobile p4 tm systems 0930a?04/13/10 954226 programmable timing control hub tm for mobile p4 tm systems 21 dimensions symbol min. max. a0.81.0 a1 0 0.05 n 56 56 a3 n d 14 14 b 0.18 0.3 n e 14 14 e d x e basic 8.00 x 8.00 8.00 x 8.00 d2 min. / max. 2.75 / 6.80 4.35 / 4.65 e2 min. / max. 2.75 / 6.80 5.05 / 5.35 l min. / max. 0.30 / 0.50 0.30 / 0.50 ics 56l tolerance symbol vlld-2 / -5 0.50 basic thermally enhanced, very thin, fine pitch quad flat / no lead plastic package dimensions 0.25 reference top v iew index area d sawn singulation anvil singulation a 0. 08 c c a3 a1 seating plane e2 e2 2 l (n -1)x e (ref.) (ref.) & n n ev en n e d2 2 d2 (re f.) & odd 1 2 e 2 (t yp.) if n & n are even (n -1)x (ref.) b thermal base n or chamfer 4x 0.6 x 0.6 max optional e d n n d d d ordering information part / order number shipping packaging package temperature 954226AGLF tubes 56-pin tssop 0 to +70 c 954226AGLFt tape and reel 56-pin tssop 0 to +70 c 954226aklf tubes 56-pin mlf 0 to +70 c 954226aklft tape and reel 56-pin mlf 0 to +70 c ?lf? to the suffix are the pb-free configuration and are rohs compliant. ?a? is the device revision designator (will not correlate with the datasheet revision).
22 954226 programmable timing control hub tm for mobile p4 tm systems innovate with idt and accelerate your future networks. contact: www.idt.com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support 408-284-6578 pcclockhelp@idt.com corporate headquarters integrated device technology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800 345 7015 +408 284 8200 (outside u.s.) asia pacific and japan idt singapore pte. ltd. 1 kallang sector #07-01/06 kolamayer industrial park singapore 349276 phone: 65-6-744-3356 fax: 65-6-744-1764 europe idt europe limited 321 kingston road leatherhead, surrey kt22 7tu england phone: 44-1372-363339 fax: 44-1372-378851 ? 2010 integrated device technology , inc. all rights reserved. product specifications subject to change without notice. idt, ic s, and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other br ands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa revision history rev. issue date who description page # 0.1 3/29/2005 jc updated ordering information from "lead free" to "annealed lead free" 18 0.2 7/14/2006 dc added mlf pinout, pin description and ordering information. 1, 4, 5, 21 a 4/12/2010 rdw 1. clean up electrical tables 2. corrected test clarification table 3. move to final

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